Title :
A low cost 100 MHz analog test bus
Author_Institution :
Telecom Microelectron. Centre, Northern Telecom Electron. Ltd., Nepean, Ont., Canada
fDate :
30 Apr-3 May 1995
Abstract :
This paper describes an on-chip analog bus whose bandwidth is limited primarily by an off-chip amplifier. It uses only a digital 3-state inverter for each bus input. The high-speed and constant low-input capacitance of this scheme make it suitable for measuring sensitive or even digital signals. For equal silicon area, the signal bandwidth is demonstrated to be 10 to 40 times that of previously reported transmission gate schemes
Keywords :
capacitance; design for testability; integrated circuit design; mixed analogue-digital integrated circuits; 100 MHz; DFT; IC design; analog test bus; bus input; digital three-state inverter; low-input capacitance; mixed-signal circuits; on-chip analog bus; signal bandwidth; Bandwidth; Capacitance; Circuit testing; Costs; Design for testability; Inverters; Operational amplifiers; Silicon; Telecommunications; Voltage;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512618
