DocumentCode :
2278764
Title :
On the decline of testing efficiency as fault coverage approaches 100%
Author :
Wang, Li C. ; Mercer, M. Ray ; Kao, Sophia W. ; Williams, Thomas W.
Author_Institution :
Texas Univ., Austin, TX, USA
fYear :
1995
fDate :
30 Apr-3 May 1995
Firstpage :
74
Lastpage :
83
Abstract :
Testing is an indispensable process to weed out the defective parts coming out of the manufacturing process. Traditionally, test generation targets on a specific fault model, usually the single stuck-at fault model, to produce tests that are expected to identify defects such as unintended shorts and opens. With this approach, the test quality relies on fortuitous detection of the non-target defects. As the quality demands and circuit sizes increase, the feasibility of test generation on a single fault model becomes questionable. In the paper, we present empirical data from experiments on ISCAS benchmark circuits to demonstrate that using traditional methods the probability of detecting nontarget defects drops rapidly as the fault coverage approaches 100%. By assuming surrogates, we explain the mechanism which produces this effect and describe a new test pattern generation approach with better testing efficiency
Keywords :
automatic testing; fault diagnosis; integrated circuit testing; logic testing; production testing; ISCAS benchmark circuits; circuit sizes; fault coverage; manufacturing process; nontarget defects; single stuck-at fault model; test pattern generation; test quality; testing efficiency; Circuit faults; Circuit testing; Contracts; Electrical fault detection; Fault detection; Fault diagnosis; Large scale integration; Logic functions; Manufacturing processes; Semiconductor device testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
ISSN :
1093-0167
Print_ISBN :
0-8186-7000-2
Type :
conf
DOI :
10.1109/VTEST.1995.512620
Filename :
512620
Link To Document :
بازگشت