Title :
The use of IDDQ testing in low stuck-at coverage situations
Author :
Maxwell, Peter C.
Author_Institution :
Hewlett-Packard Co., USA
fDate :
30 Apr-3 May 1995
Abstract :
An unresolved issue in IC testing is what mix of coverages of different types of test is required in order to achieve a given quality goal. This paper investigates the interaction between IDDQ and stuck-at coverage and examines the use of IDDQ to increase effective stuck-at coverage, particularly in situations where the graded coverage is lower than the desired goal. Empirical data is presented which examines the extent to which a varying number of IDDQ tests can detect parts which would fail stuck-at tests. This leads to development of a composite metric, based on stuck-at coverage, which allows a tradeoff to be made between adding further logic tests and adding IDDQ tests
Keywords :
CMOS logic circuits; application specific integrated circuits; automatic testing; fault diagnosis; integrated circuit testing; logic testing; ASIC; IC testing; IDDQ testing; composite metric; graded coverage; logic tests; quality goal; stuck-at coverage situations; Circuit faults; Circuit testing; Companies; Data mining; Information analysis; Integrated circuit technology; Integrated circuit testing; Logic testing; Probability; Statistics;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512621
