Cyclic stress tests for full scan circuits

Author

Dabholkar, V. ; Chakravarty, S. ; Najm, F. ; Patel, J.

Author_Institution

State Univ. of New York, Buffalo, NY, USA

fYear

1995

fDate

30 Apr-3 May 1995

Firstpage

89

Lastpage

94

Abstract

To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in process the circuit needs to be stressed for an extended period of time. This requires computation of cyclic input sequences to stress the circuit. A taxonomy of stress related problems for full scan circuits is presented. It is shown that there are efficient ways to compute the sequences for many variations of monitored burn-in problems. Preliminary experimental results on ISCAS89 benchmark circuits are presented

Keywords

CMOS logic circuits; VLSI; boundary scan testing; integrated circuit reliability; integrated circuit testing; logic testing; CMOS; IC reliability; ISCAS89 benchmark circuits; MCMs; VLSI; burn-in process; cyclic input sequences; cyclic stress tests; full scan circuits; fully testable unpackaged dies; monitored burn-in problems; stress related problems; Circuit testing; Clocks; Combinational circuits; Monitoring; Power dissipation; Registers; Stress; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1995. Proceedings., 13th IEEE

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7000-2

Type

conf

DOI

10.1109/VTEST.1995.512622

Filename

512622