An apparatus for pseudo-deterministic testing

In this paper we propose a new apparatus for embedding deterministic patterns in pseudo-random sequences, with application to at-speed BIST. We employ an arbitrary length Shift Register driven by a LFSR (LFSR/SR) with the size of the LFSR dependent only on the number of care bits in any test vector. We provide an efficient method to compute positions of bit-patterns at arbitrarily chosen tap configurations in the LFSR/SR sequence. Hence, one can make an optimal choice of test segments (seeds) while taking inherent advantage of don´t care bits in test vectors, say corresponding to random pattern resistant faults. The length of the LFSR/SR can be arbitrarily increased to feed several interconnected logic blocks such that all the care bits of any deterministic test vector can be predictably generated without compromising computational efficiency