DocumentCode
2278874
Title
Arithmetic built-in self test for high-level synthesis
Author
Mukherjee, N. ; Kassa, M. ; Rajski, J. ; Tyszer, J.
Author_Institution
Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
fYear
1995
fDate
30 Apr-3 May 1995
Firstpage
132
Lastpage
139
Abstract
In this paper, we propose an entirely new Built-in Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to generate test vectors and compact test responses. The paper employs state coverage to evaluate testability in an abstract level, and subsequently, use it to guide the synthesis of testable circuits
Keywords
built-in self test; high level synthesis; integrated circuit testing; logic CAD; logic testing; abstract level; arithmetic blocks; arithmetic built-in self test; compact test responses; data path architectures; high-level synthesis; state coverage; test vectors; testability; testable circuit synthesis; Adders; Arithmetic; Automatic testing; Circuit synthesis; Circuit testing; Control system synthesis; High level synthesis; Registers; System testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location
Princeton, NJ
ISSN
1093-0167
Print_ISBN
0-8186-7000-2
Type
conf
DOI
10.1109/VTEST.1995.512628
Filename
512628
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