DocumentCode :
2278927
Title :
On the study of loop profiles in improving the sweep stiffness of wire bond
Author :
Kung, H.K. ; Huang, C.H. ; Chanyshev, A.I.
Author_Institution :
Graduate Inst. of Mechatronic Eng., Cheng Shiu Univ., Kaohsiung
fYear :
2006
fDate :
6-8 Dec. 2006
Firstpage :
472
Lastpage :
477
Abstract :
The deflection of gold wire bonds during the encapsulation of IC packaging can seriously cause wire crossover and shorting. Up to now, there is no (standard) algorithm has been proposed to decide the better bond looping system for optimal adjusting the parameters of wire bonder to obtain lower deflection of wire bond. The wire sweep experiment is developed to define the sweep stiffness of wire bond in the related studies. The sweep stiffness of wire bond is defined to be the index of sweep resistance to drag force during the transfer molding process. Higher sweep stiffness of wire bond possesses lower wire sweep and thereby higher yield rate of IC packaging. The sweep stiffness of three bond modes, Q-loop, S-loop and M-loop bonds is studied in this paper. The results show the Q-loop bond has the highest sweep stiffness values than those of the S-loop and M-loop bonds for fixed bond spans and bond heights. The sweep stiffness of S-loop and M-loop bonds, mostly used for longer connections or crossing another chip in multichip module/3-dimensional packages has found to be affected significantly by their kinking numbers within a bond. The experimental results points out that the M-loop bond has better sweep resistance than the S-loop bond does. The increment in the sweep stiffness could be up to 13-75% depend on the bond span and bond height used.
Keywords :
elastic constants; encapsulation; integrated circuit packaging; lead bonding; multichip modules; 3D packages; M-loop bond; Q-loop bond; S-loop bond; drag force; integrated circuit packaging; loop profiles; multichip modules; sweep resistance; sweep stiffness; transfer molding; wire bonding; wire crossover; Bonding forces; Drag; Electronics packaging; Equations; Gold; Integrated circuit modeling; Integrated circuit packaging; Semiconductor device packaging; Transfer molding; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2006. EPTC '06. 8th
Conference_Location :
Singapore
Print_ISBN :
1-4244-0664-1
Electronic_ISBN :
1-4244-0665-X
Type :
conf
DOI :
10.1109/EPTC.2006.342759
Filename :
4147288
Link To Document :
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