Enabling SPICE-type modeling of the thermal properties of 3D-stacked ICs

Technologies enabling 3D-stacking of chips with through-Si interconnects are becoming of increased interest. These 3D-stacking technologies result in strongly reduced system dimension and hence a significant increase of power density. The capacity of the system to efficiently transport and dissipate heat is of major importance to assure functionality and reliability of the system. This paper reports on the thermal resistance modeling of 3D-die stacks, that are built according to IMECs 3D-SIC (3D-Stacked IC) process flow. The main result of this work is a semi-analytical parametric thermal resistance model that may be used to estimate the thermal resistance of any given 3D-SIC geometry by solving a thermal resistance network (SPICE-type simulation)