DocumentCode
2279036
Title
Switch-level modeling of transistor-level stuck-at faults
Author
Lidén, Peter ; Dahlgren, Peter
Author_Institution
Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
fYear
1995
fDate
30 Apr-3 May 1995
Firstpage
208
Lastpage
213
Abstract
Two new switch-level algorithms with efficient management of unknown values are evaluated with respect to their fault modeling capability. The degradation of confidence in fault detection measures owing to unknown (X) output values is discussed and a strategy to quantify this uncertainty is proposed. It is demonstrated that this uncertainty can be decreased significantly when the node model is extended to include two resistances
Keywords
CMOS logic circuits; circuit analysis computing; fault diagnosis; integrated circuit modelling; integrated circuit testing; logic testing; CMOS circuits; confidence degradation; fault detection measures; fault modeling capability; node model; switch-level algorithms; switch-level modeling; transistor-level stuck-at faults; uncertainty quantification; unknown output values; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Feedback loop; MOSFETs; Semiconductor device modeling; Switches; Switching circuits; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location
Princeton, NJ
ISSN
1093-0167
Print_ISBN
0-8186-7000-2
Type
conf
DOI
10.1109/VTEST.1995.512639
Filename
512639
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