DocumentCode
2279058
Title
VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits
Author
Nair, Rajesh ; Ha, Dong Sam
Author_Institution
Synopsys Inc., Mountain View, CA, USA
fYear
1995
fDate
30 Apr-3 May 1995
Firstpage
221
Lastpage
226
Abstract
VISION is an efficient parallel pattern fault simulator for synchronous sequential circuits. VISION is based on an earlier fault simulator called PARIS which was the first and a highly efficient parallel pattern fault simulator. In this paper, we propose four new heuristics which substantially speed up the parallel pattern fault simulation for synchronous sequential circuits. According to our experiments, our fault simulator, VISION, which incorporates the four heuristics, is about 1.6 times faster than PARIS for 16 benchmark circuits
Keywords
VLSI; circuit analysis computing; digital simulation; fault diagnosis; flip-flops; integrated circuit testing; logic testing; sequential circuits; VISION; VLSI; benchmark circuits; heuristics; parallel pattern fault simulator; synchronous sequential circuits; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Flip-flops; Logic testing; Sequential circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location
Princeton, NJ
ISSN
1093-0167
Print_ISBN
0-8186-7000-2
Type
conf
DOI
10.1109/VTEST.1995.512641
Filename
512641
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