DocumentCode :
2279210
Title :
A partial scan methodology for testing self-timed circuits
Author :
Khoche, Ajay ; Brunvand, Erik
Author_Institution :
Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
fYear :
1995
fDate :
30 Apr-3 May 1995
Firstpage :
283
Lastpage :
289
Abstract :
This paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and requires fewer storage elements to be made scannable than full scan approaches with similar fault coverage. A new method is proposed to test the sequential network in this partial scan environment. Experimental data is presented to show that high fault coverage is possible using this method with only a subset of storage elements being made scannable
Keywords :
asynchronous circuits; boundary scan testing; design for testability; integrated circuit testing; integrated logic circuits; logic design; logic testing; control section testing; fault coverage; macromodule based circuits; partial scan methodology; self-timed circuits; sequential network; stuck-at faults; Asynchronous circuits; Automatic testing; Centralized control; Circuit faults; Circuit testing; Clocks; Computer science; Delay; Distributed control; Protocols;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
ISSN :
1093-0167
Print_ISBN :
0-8186-7000-2
Type :
conf
DOI :
10.1109/VTEST.1995.512650
Filename :
512650
Link To Document :
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