On the design of at-speed testable VLSI circuits

In this paper, a new design-for-testability technique for sequential circuits is presented. This technique may be considered as an alternative to full scan. The fault coverages obtained with this technique are comparable to those produced by full scan techniques. However, the present method improves full scan in several ways. The application test time of a device is reduced to that of applying parallel vectors at the operational speed. This characteristic of applying test vectors at the operational speed has a positive impact on the test quality. Indeed, a stuck-at test, applied at the operational speed of the circuit, identifies more defective chips than the same test applied at a lower speed. Furthermore, the timing and the area overheads, which are often considered to be serious disadvantages of DFT techniques, are in this case acceptable. With this method, all FFs are replaced with XFF gates. The XFF gate is similar to a T flip-flop without feedback. However, in some cases, when observability problems are still important, a probe observation point is inserted at the pseudo-primary inputs (PPIs)