• DocumentCode
    2279256
  • Title

    Test pattern generation for IDDQ: increasing test quality

  • Author

    Dalpasso, Marcello ; Favalli, Michele ; Olivo, Piero

  • Author_Institution
    Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
  • fYear
    1995
  • fDate
    30 Apr-3 May 1995
  • Firstpage
    304
  • Lastpage
    309
  • Abstract
    So far, the test pattern generation for IDDQ testing has been performed without considering the value of the faulty current in comparison with the minimum current that is detectable as a fault: this approach will be shown to be misleading, since it actually gives optimistic coverage evaluation. Then, this work presents an ATPG strategy that targets the highest valves of current during the fault activation, in such a way that either a higher fault coverage can be obtained or a less accurate sensor can be used
  • Keywords
    CMOS logic circuits; automatic testing; integrated circuit testing; logic testing; ATPG strategy; IDDQ testing; fault coverage; quiescent power supply current monitoring; test pattern generation; Automatic test pattern generation; Bridges; Circuit faults; Circuit testing; Fault detection; Joining processes; Logic gates; Logic testing; Performance evaluation; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1995. Proceedings., 13th IEEE
  • Conference_Location
    Princeton, NJ
  • ISSN
    1093-0167
  • Print_ISBN
    0-8186-7000-2
  • Type

    conf

  • DOI
    10.1109/VTEST.1995.512653
  • Filename
    512653
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2279256