• DocumentCode
    2279267
  • Title

    Compact test generation for bridging faults under IDDQ testing

  • Author

    Reddy, Remata S. ; Pomeranz, Irith ; Reddy, Sudhakar M. ; Kajihara, Seiji

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
  • fYear
    1995
  • fDate
    30 Apr-3 May 1995
  • Firstpage
    310
  • Lastpage
    316
  • Abstract
    We propose a procedure to generate compact test sets for bridging faults under IDDQ testing. Several techniques are employed to achieve compact test sets. Heuristics developed for stuck-at faults are shown to be effective in this context. The techniques especially designed for bridging faults are based on the observation that the yet-undetected faults can be represented using sets of lines and that a minimum test set size is obtained if the line sets representing yet-undetected faults are halved with every additional test vector. Logic blocks called bit-adders allow the partitioning of the line sets using a test generator for stuck-at faults, without having to determine in advance how the lines in a given set will be divided. Thus partitioning can be performed in a cost effective way for any line set size. Experimental results show that the test sets generated by the proposed procedure are smaller than those obtained by previously proposed procedures
  • Keywords
    CMOS logic circuits; fault location; integrated circuit testing; logic partitioning; logic testing; IDDQ testing; bit-adders; bridging faults; compact test generation; partitioning; stuck-at faults; Bridge circuits; Circuit faults; Circuit testing; Current supplies; Fault detection; Fault diagnosis; Feedback circuits; Logic; Switches; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1995. Proceedings., 13th IEEE
  • Conference_Location
    Princeton, NJ
  • ISSN
    1093-0167
  • Print_ISBN
    0-8186-7000-2
  • Type

    conf

  • DOI
    10.1109/VTEST.1995.512654
  • Filename
    512654