Title :
CURRENT: a test generation system for IDDQ testing
Author :
Mahlstedt, Udo ; Alt, Jürgen ; Heinitz, Matthias
Author_Institution :
Inst. fur Theor. Elektrotech., Hannover Univ., Germany
fDate :
30 Apr-3 May 1995
Abstract :
This paper presents an IDDQ test generation system for scan-based circuits, called CURRENT. A library-based fault modeling strategy is used to specify a realistic target fault set, which encompasses intra-gate shorts (for example stuck-on faults, gate-drain shorts) as well as inter-gate shorts (bridging faults). CURRENT consists of a fault simulator and a deterministic test generator. The fault simulator can be used to determine the fault coverage of a given test set or to generate test patterns for easy-to-detect leakage faults. The deterministic test generator is able to generate tests for hard-to-detect leakage faults and to identify redundant leakage faults. Furthermore, CURRENT is able to generate small test sets through the use of a new test set compaction technique, thus reducing the total test application time for IDDQ testing. Experimental results show that CURRENT is able to generate small test sets with a test efficiency of 100% for each of the benchmark circuits with up to 2,400,000 considered leakage faults
Keywords :
CMOS logic circuits; automatic testing; boundary scan testing; fault diagnosis; fault location; integrated circuit testing; logic testing; CURRENT test system; IDDQ testing; bridging faults; deterministic test generator; fault coverage; fault simulator; gate-drain shorts; inter-gate shorts; intra-gate shorts; leakage faults; library-based fault modeling strategy; scan-based circuits; stuck-on faults; test application time reduction; test generation system; test set compaction technique; Benchmark testing; Circuit faults; Circuit testing; Compaction; Integrated circuit technology; Integrated circuit testing; Semiconductor device modeling; Switches; System testing; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512655