DocumentCode
2279551
Title
A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers
Author
Brown, Steve ; Gutierrez, German ; Nelson, Reed ; VanKrevelen, C.
Author_Institution
AMCC, San Diego, CA, USA
fYear
1995
fDate
30 Apr-3 May 1995
Firstpage
467
Lastpage
471
Abstract
An integrated circuit for high speed testing which provides precision edge timing and control for three complete channels is described. It consists of nine timing verniers of 40 pS time-step, 80 pS accuracy and 2 nS full range, and all the logic required to configure the drive waveforms and the strobe of the returning signals. The system clock frequency into the IC is 500 MHz
Keywords
automatic test equipment; clocks; emitter-coupled logic; logic arrays; programmable controllers; timing; 40 ps; 500 MHz; ECL; drive waveforms; gate array; high speed testing; precision edge timing; returning signals; system clock frequency; timing verniers; triple channel ATE controller; Circuit testing; Clocks; Control systems; Electronic equipment testing; High speed integrated circuits; Integrated circuit testing; Logic circuits; Logic testing; System testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location
Princeton, NJ
ISSN
1093-0167
Print_ISBN
0-8186-7000-2
Type
conf
DOI
10.1109/VTEST.1995.512676
Filename
512676
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