Unified delay analysis for on-chip RLCG interconnects for ramp input using fourth order transfer function

Earlier only the delay caused due to the presence of gates was considered to be an important issue, but now with decreasing feature size and increasing complexity, on-chip interconnect delay has acquired prominence for incremental performance-driven layout synthesis. In this paper, we have obtained an analytical delay model, for RLCG interconnect lines, that in addition to preserving the effectiveness of the previous RLC interconnect models, improves the accuracy for deep submicron technologies that are used at higher frequencies. As the existing works till date, have mostly focused on RC and RLC interconnects with step signal as its input, this approach towards RLCG interconnects is a challenge in itself. In this paper, we have put forward an analytical model, which could accurately capture the on-chip interconnect delay. As we move onto higher frequency ranges, of the order of GHz, the effects of shunt conductance can not be ignored, as that provides a measure of the possible leakage. Due to these reasons, we have derived our on-chip interconnect delay metric considering distributed RLCG segments, rather than sticking to the conventional RLC and RC. The experimental results reveal that our model matches very well with the delay calculations, obtained using SPICE, resulting in an error of less than 4%.