FPGA implementation of a sequence separation algorithm based on a generalized delayed signal cancelation method

A system-on-chip fundamental-frequency positive-sequence detector based on FPGA technology is proposed in this paper. The method is implemented by using the instantaneous alphabeta voltage vector and also this vector delayed in time. A mathematical transformation is then implemented through which the original and delayed voltage vectors are combined. Cascaded transformations are then used for eliminating the fundamental-frequency negative-sequence vector as well as chosen positive- and negative-sequence harmonic vector components and thus, for accurately obtaining the fundamental-frequency positive-sequence voltage vector. The output of the last transformation block is input to a synchronous reference frame phase-locked-loop (SRF-PLL) for detecting frequency and position of the positive-sequence vector. A discrete fixed-point FPGA-based design of the method described is proposed. The approach is implemented and tested with a Spartan 3E (XC3S500) FPGA.