DocumentCode :
2280394
Title :
Coping with process variations in ultra-low power CMOS analog integrated circuits
Author :
Wang, Z. ; Savci, H.S. ; Griggs, J.D. ; Dogan, N.S. ; Arvas, E.
Author_Institution :
Dept. of ECE, NC A & T State Univ., Greensboro, NC
fYear :
2007
fDate :
22-25 March 2007
Firstpage :
54
Lastpage :
57
Abstract :
Ultra-low power analog/RF CMOS circuits are critical for battery-operated electronics. Low-supply voltage and current requirements are met by operating MOS transistors in weak to moderate inversions and very small overdrive voltages. The advantage of this technique comes with the price of complex and aggressive design burdens to be achieved. Therefore designers should have control over the behavior of their circuits such as the process, supply, and temperature variations. This paper presents a technique, which dynamically adjusts the threshold voltage to overcome the process and supply variation. Proposed technique (DTMOS) is used for digital and analog/RF designs. The simulation results show that with the proposed technique the variations in drain current and transconductance due to uncertainty of the process parameters and voltage deviations in the power supplies could be successfully compensated.
Keywords :
CMOS analogue integrated circuits; low-power electronics; semiconductor process modelling; DTMOS; process variations; ultra low power CMOS analog integrated circuits; Analog circuits; Batteries; CMOS analog integrated circuits; CMOS process; Dynamic range; Dynamic voltage scaling; MOS devices; MOSFET circuits; Photonic band gap; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoutheastCon, 2007. Proceedings. IEEE
Conference_Location :
Richmond, VA
Print_ISBN :
1-4244-1028-2
Electronic_ISBN :
1-4244-1029-0
Type :
conf
DOI :
10.1109/SECON.2007.342853
Filename :
4147383
Link To Document :
بازگشت