• DocumentCode
    2281008
  • Title

    A method for die-scale simulation of CMP planarization

  • Author

    Thye-Lai Tung

  • Author_Institution
    TCAD, Intel Corp., Santa Clara, CA, USA
  • fYear
    1997
  • fDate
    8-10 Sept. 1997
  • Firstpage
    65
  • Lastpage
    68
  • Abstract
    Chemical-Mechanical Polishing (CMP) is well known for its planarization capability. However, it suffers from long-range non-uniformity due to its sensitivity to pattern density. This paper shows that, by using basic building blocks and formulation techniques, CMP simulation can be done on a large dimension, namely the whole die.
  • Keywords
    polishing; semiconductor process modelling; CMP planarization; chemical-mechanical polishing; die-scale simulation; Chemical processes; Dielectrics; Educational institutions; Image sampling; Numerical models; Planarization; Sampling methods; Semiconductor device modeling; Shape; Slurries;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97., 1997 International Conference on
  • Conference_Location
    Cambridge, MA, USA
  • Print_ISBN
    0-7803-3775-1
  • Type

    conf

  • DOI
    10.1109/SISPAD.1997.621337
  • Filename
    621337
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2281008