FPGA implementation of the timing synchronization in preamble based OFDM system

Orthogonal frequency division multiplexing (OFDM) is an effective modulation technique for high-rate transmission over frequency selective fading channels. However, just because of its orthogonality, OFDM systems are also extremely sensitive and vulnerable to synchronization errors. In this paper, we investigate a scheme especially for symbol synchronization utilizing the special training structure, which can be used in preamble-based OFDM system. Without loss the generality, IEEE 802.11a WLAN system will be researched as the model. The algorithms of match filter and cyclic prefix (CP) are combined to achieve good symbol timing synchronization. The former algorithm is to determine the short training symbol´s precise end of the burst transmission, and then the latter algorithm will confirm the valid data of data symbols. At last, we present the timing synchronization´s FPGA implementation