Power Supply Noise Analysis in DSM Circuits

The continuous technology advance into the VDSM regime has brought the noise and signal integrity issues into the spotlight. It seems to be more important to estimate the power supply noise efficiently and accurately than other design metrics such as area, timing and power. At the same time, the capacitive and inductive effect should no longer be ignored in the noise analysis process. In the work, a GA-based statistical modeling technique is presented to find the worst-case time-domain voltage variation in VLSI power distribution network including inductive and resistive effects. And, the statistical power supply noise is also mapped into perturbation of the macroblock delay. Experimental results are put together with SPICE simulations, and show the validity of the method.