Title :
Proceedings. 2005 International Conference on Computer Design
Abstract :
The following topics are dealt with: processor design; interconnect prediction; interconnect optimization; system-level architecture; power aware system design; physical-aware system-level analysis and synthesis; SoC test methods; reliable circuit design; high level synthesis; SoC verification; low power circuit architecture; formal verification; cache memory architecture; gate timing; power analysis; low voltage design; sequential circuits; delay fault models; new memory technologies; future VLSI technologies; RF wireless technologies; and logic optimization.
Keywords :
VLSI; cache storage; formal verification; high level synthesis; integrated circuit design; integrated circuit interconnections; logic design; low-power electronics; memory architecture; microprocessor chips; system-on-chip; RF wireless technologies; SoC test methods; SoC verification; VLSI technologies; cache memory architecture; delay fault models; formal verification; gate timing; high level synthesis; integrated circuit design; interconnect optimization; interconnect prediction; logic optimization; low power circuit architecture; low voltage design; memory technologies; physical-aware system-level analysis; power analysis; power aware system design; processor design; sequential circuits; system-level architecture; system-level synthesis; system-on-chip;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7695-2451-6
DOI :
10.1109/ICCD.2005.2
