DocumentCode :
2281665
Title :
A new diffusion algorithm during oxidation which can handle both phosphorus pile-up and boron segregation at Si-SiO/sub 2/ interface
Author :
Sakamoto, H. ; Kumashiro, S.
Author_Institution :
ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan
fYear :
1997
fDate :
8-10 Sept. 1997
Firstpage :
81
Lastpage :
84
Abstract :
A new simulation algorithm during oxidation which can handle both the phosphorus (P) pile-up and the boron (B) segregation has been proposed. In this algorithm, an interlayer (IL) is placed at Si-SiO/sub 2/ interface in order to have P pile-up. The interface is moved according to the Si consumption during a time step and a new interface is generated at the end of the consumed Si region. A region between an old and a new IL is defined as a transition layer (TL). A diffusion equation is solved inside the TL using local effective diffusion constants in order to fully redistribute the impurities. By using this "diffusion in the TL", the P piled up in the old IL may move through the TL and re-piles up into the new IL, and B segregation can be simulated accurately. The V/sub th/-V/sub sub/ characteristics of an actual buried channel pMOSFET which is simulated using the proposed algorithm agrees well with the experiment.
Keywords :
MOSFET; boron; buried layers; diffusion; elemental semiconductors; impurity distribution; oxidation; phosphorus; semiconductor process modelling; semiconductor-insulator boundaries; silicon; silicon compounds; surface segregation; B segregation; P pileup; Si; Si consumption; Si oxidation; Si-SiO/sub 2/ interface; Si:B,P-SiO/sub 2/; buried channel pMOSFET; diffusion algorithm; diffusion equation; impurity redistribution; interface interlayer; local effective diffusion constants; threshold voltage substrate voltage characteristics; transition layer; Boron; Equations; Etching; Hafnium; Impurities; Laboratories; MOSFET circuits; National electric code; Oxidation; Ultra large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97., 1997 International Conference on
Conference_Location :
Cambridge, MA, USA
Print_ISBN :
0-7803-3775-1
Type :
conf
DOI :
10.1109/SISPAD.1997.621341
Filename :
621341
Link To Document :
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