Are today´s verification tools able to handle current design challenges?

Summary form only given. With the ever increasing growth of size and complexity of digital designs, tools have just kept pace. Design engineers bare the brunt of the problem. To make use of dynamic verification, designers invest as much or more time into their testbenches as they do in the design they are creating. For static or formal verification, large designs with complex state spaces have challenged even the most powerful formal tools. What changes are coming in the design and EDA spaces that will improve this situation? What is the right mix of dynamic and static verification for the future?.