A methodology for full-chip extraction of interconnect capacitance using Monte Carlo-based field solvers

We present a full-chip extraction methodology for evaluating self-capacitance of interconnects in complex digital ICs. We propose that a Monte Carlo-based field solver be used to evaluate critical net capacitances and to accurately characterize a faster, less accurate empirical extractor. The fast extractor can then be used to find noncritical net capacitances. To facilitate a priori partitioning of nets into critical and noncritical categories, we have developed a procedure for estimating absolute computational error of any capacitance extractor. We also report that Monte Carlo extractors can efficiently evaluate coupling capacitance between IC nets. In this case, statistical error cancellation occurs during a subsequent circuit simulation.