Physical synthesis of energy-efficient networks-on-chip through topology exploration and wire style optimization

Power consumption has become one of the first order design considerations of the nano-scale VLSI designs. In this paper, we propose a methodology to synthesize energy-efficient networks-on-chip (NoCs). Our methodology features three key characters. First, we adopt a multi-commodity flow formulation to unify network topologies, physical embedding, and wire style optimizations. Second, we utilize a variety of interconnect wire styles to achieve high performance low power on-chip communication. Third, we heuristically explore a large design space of network topologies. Experiments on a homogeneous communication demand model demonstrate that for a 4 × 4 NoC with torus topology, our methodology can achieve a power saving up to 35%.