DocumentCode
2282040
Title
Concurrent core test for test cost reduction using merged test set and scan tree
Author
Zeng, Gang ; Ito, Hideo
Author_Institution
Graduate Sch. of Sci. & Technol., Chiba Univ., Japan
fYear
2005
fDate
2-5 Oct. 2005
Firstpage
143
Lastpage
146
Abstract
A novel concurrent core test approach is proposed to reduce the test cost of SOC. Prior to the application of test, the test sets corresponding to cores under test (CUT) are merged by using the proposed merging algorithm to obtain a minimum size of merged test set. During test, the proposed scan tree architecture is employed to support the concurrent core test using the merged test set. The approach achieves concurrent core test with one scan input and low hardware overhead. Moreover, the approach does not need any additional test generation, and it can be used in conjunction with general compression/decompression techniques to further reduce test cost. Experimental results for ISCAS 89 benchmarks have proven the efficiency of the proposed approach.
Keywords
integrated circuit testing; logic testing; system-on-chip; compression techniques; concurrent core test; cores under test; decompression techniques; merged test set; scan tree architecture; system-on-chip; test cost reduction; Automatic test pattern generation; Benchmark testing; Circuit testing; Costs; Design methodology; Hardware; Intellectual property; Merging; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN
0-7695-2451-6
Type
conf
DOI
10.1109/ICCD.2005.39
Filename
1524144
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