A computationally stable quasi-empirical compact model for the simulation of MOS breakdown in ESD-protection circuit design

Author

Shiang Liang Lim ; Xin Yi Zhang ; Zhipeng Yu ; Beebe, S. ; Dutton, R.W.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1997

fDate

8-10 Sept. 1997

Firstpage

161

Lastpage

164

Abstract

This paper presents a simple-to-implement, semi-empirical model for circuit-level simulation of the MOS breakdown region, with application in ESD-protection circuit design. A new formulation for the multiplicative factor M, used to model avalanche current generation, shows good convergence properties when used in circuit simulators. The effects of source/drain series resistance, substrate resistance, and the parameters of the new M expression are described. We describe how to calibrate the parameters for an NMOS device. Finally, we compare the simulated results with experimental data.

Keywords

MOSFET; avalanche breakdown; circuit analysis computing; electrostatic discharge; protection; semiconductor device models; ESD protection circuit design; MOS breakdown simulation; NMOS device; avalanche current generation; circuit-level simulation; computationally stable model; convergence properties; multiplicative factor; quasi-empirical compact model; source/drain series resistance; substrate resistance; Bipolar transistors; Circuit simulation; Circuit synthesis; Computational modeling; Convergence; Electric breakdown; Intrusion detection; MOS devices; Protection; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97., 1997 International Conference on

Conference_Location

Cambridge, MA, USA

Print_ISBN

0-7803-3775-1

Type

conf

DOI

10.1109/SISPAD.1997.621362

Filename

621362