Title :
Evaluating FPGAs: capacity and utilization
Author :
Small, B. ; Bodmer, A. ; Mourad, S.
Author_Institution :
Dept. of Electr. Eng., Santa Clara Univ., CA, USA
Abstract :
The authors present the experimental results of a study on the effective capacity of a set of field programmable gate array (FPGA) devices and the influence of different circuit types on their utilization. A practical mix of benchmark circuits were used with several different FPGAs. The results indicate that (1) optimization is necessary to effect efficient device utilization, (2) devices with built in flip-flops are not efficient in implementing combinational circuits, and (3) the percentage of flip-flops in a circuit should match the percentage of flip-flops in the total device to maximize gate density. A graphical model is presented to interpret these results
Keywords :
flip-flops; logic arrays; logic testing; benchmark circuits; device utilization; field programmable gate arrays; flip-flops; gate density; graphical model; Circuit simulation; Combinational circuits; Field programmable gate arrays; Flip-flops; Graphical models; Logic arrays; Logic devices; Microprocessors; Multiplexing; Routing;
Conference_Titel :
Computers and Communications, 1993., Twelfth Annual International Phoenix Conference on
Conference_Location :
Tempe, AZ
Print_ISBN :
0-7803-0922-7
DOI :
10.1109/PCCC.1993.344473
