Scalability Study of Fully Planarized Hybrid Floating Gate Flash Memory Cells with High-k IPD

Scaling of floating gate NAND flash will require switching from conventional control gate wrap-around cells to fully planar memory cells. Due to the low coupling ratio of these cells, both a metal floating gate and high-k IPD are required, and parasitic capacitances in the memory array lead to a further drop in coupling ratio. We study the scalability of these fully planar poly/metal floating gate memory cells below the 25nm node by 3D capacitance and programming simulations. These indicate the importance of using air gap processing for sub-25nm nodes and of the metal floating gate/high-k stack. Assuming ideal air gap processing, we show that 10 nm planar cells can be made functional using the currently available TiN/Al₂O₃ material system for FG/IPD.