Assertion checking of behavioral descriptions with nonlinear solver

Verification has become the major bottleneck of the design process. According to the latest report of the International Technology Roadmap for Semiconductors, the challenge is to develop new design-for-verifiability techniques and verification methods for higher levels of abstraction. Several design-for-verifiability methodologies (DFV) have been proposed and assertion-based verification (ABV) is one of the most promising. In order to automatically verify assertions at the higher abstraction levels, it is necessary to improve the performances and capabilities of current constraint solvers. This paper presents a new technique based on nonlinear solvers that automatically checks assertions in behavioral descriptions of hardware systems. These descriptions are modeled with a set of integer polynomial inequalities. The technique provides better results than SAT solvers and it is applied to real designs, such as Viterbi decoders or vocoder digital filters.