DocumentCode
2282356
Title
Scaling Challenges in NAND Flash Device toward 10nm Technology
Author
Lee, Seokkiu
Author_Institution
R&D, Hynix Semicond. Inc., Icheon, South Korea
fYear
2012
fDate
20-23 May 2012
Firstpage
1
Lastpage
4
Abstract
The scaling of floating gate cell has been the key driving force in NAND flash market growth over the past two decades. However, the scaling of conventional floating gate technology below 20nm is looking to be very difficult due to some physical and electrical issues. Critical issues of scaling in NAND flash memory technology below 20nm are reviewed. The possible solutions for overcoming scaling challenges are introduced. With these solutions, floating gate NAND flash cell could be shrunk down close to 10nm dimension.
Keywords
NAND circuits; flash memories; logic gates; NAND flash device; NAND flash market growth; NAND flash memory technology; conventional floating gate technology; floating gate NAND flash cell; floating gate cell scaling; key driving force; scaling challenges; size 10 nm; Air gaps; Couplings; Flash memory; Interference; Logic gates; Nonvolatile memory; Shape;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2012 4th IEEE International
Conference_Location
Milan
Print_ISBN
978-1-4673-1079-6
Type
conf
DOI
10.1109/IMW.2012.6213636
Filename
6213636
Link To Document