A functional reconfigurable architecture and compiler for adaptive computing

Many computationally intensive tasks spend nearly all of their execution time within a small fraction of the executable code. Substantial gains can be achieved by allowing the configuration and fundamental operations of a processor to adapt to these frequently accessed portions. A method is presented which improves the performance of many computationally intensive tasks by utilizing information extracted at compile-time to synthesize new operations which augment the functionality of a core processor. The newly synthesized operations are targeted for RAM-based field-programmable gate array (FPGA) devices which provide a mechanism for fast processor reconfiguration. A proof-of-concept system called PRISM, consisting of a specialized C configuration compiler and a reconfigurable hardware platform, is presented. Compilation and performance results are provided which confirm the concept viability, and demonstrate significant speed-up over conventional general-purpose architectures