Title :
Low-power design of 90-nm SuperH™ processor core
Author :
Yamada, Tetsuya ; Abe, Masahide ; Nitta, Yusuke ; Ogura, Kenji ; Kusaoke, Manabu ; Ishikawa, Makoto ; Ozawa, Motokazu ; Takada, Kazumasa ; Arakawa, Fumio ; Nishii, Osamu ; Hattor, Toshihiro
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A low-power SuperH™ embedded processor core, the SH-X2, has been designed in 90-nm CMOS technology. The power consumption was reduced by using hierarchical fine-grained clock gating to reduce the power consumption of the flip-flops and clock-tree, synthesis and a layout that support implementation of the clock gating, and several-level power evaluations for RTL refinement. With this clock gating and RTL refinement, the power consumption of the clock-tree and flip-flops was reduced by 35% and 59%, including the process shrinking effects, respectively. As a result, the SH-X2 achieved 6,000 MIPS/W using a Renesas low-power process with lowered voltage. Its performance-power efficiency was 25% better than that of a 130-nm-process SH-X.
Keywords :
CMOS digital integrated circuits; clocks; flip-flops; integrated circuit layout; low-power electronics; microprocessor chips; 90 nm; CMOS technology; RTL refinement; Renesas low-power process; SuperH processor core; clock-tree; embedded processor core; fine-grained clock gating; flip-flops; low-power design; power consumption reduction; process shrinking effects; CMOS process; CMOS technology; Circuits; Clocks; Digital signal processing; Energy consumption; Home appliances; Random access memory; Ultra large scale integration; Voltage;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN :
0-7695-2451-6
DOI :
10.1109/ICCD.2005.72