DocumentCode
2282412
Title
Algorithmic and architectural design methodology for particle filters in hardware
Author
Sankaranarayanan, Aswin C. ; Chellappa, Rama ; Srivastava, Ankur
Author_Institution
Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
fYear
2005
fDate
2-5 Oct. 2005
Firstpage
275
Lastpage
280
Abstract
In this paper, we present algorithmic and architectural methodology for building particle filters in hardware. Particle filtering is a new paradigm for filtering in presence of nonGaussian nonlinear state evolution and observation models. This technique has found wide-spread application in tracking, navigation, detection problems especially in a sensing environment. So far most particle filtering implementations are not lucrative for real time problems due to excessive computational complexity involved. In this paper, we re-derive the particle filtering theory to make it more amenable to simplified VLSI implementations. Furthermore, we present and analyze pipelined architectural methodology for designing these computational blocks. Finally, we present an application using the bearing only tracking problem and evaluate the proposed architecture and algorithmic methodology.
Keywords
VLSI; digital filters; parallel architectures; particle filtering (numerical methods); pipeline processing; VLSI implementation; algorithmic design methodology; bearing only tracking problem; computational complexity; nonGaussian nonlinear state evolution; particle filtering; pipelined architectural methodology; Design methodology; Filtering algorithms; Hardware; Kalman filters; Navigation; Nonlinear filters; Particle filters; Particle tracking; State estimation; Target tracking;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN
0-7695-2451-6
Type
conf
DOI
10.1109/ICCD.2005.20
Filename
1524165
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