Architecture of 3D Memory Cell Array on 3D IC

High density 3D memory cell array using SGT(Surrounding Gate Transistor) on 3D IC is proposed. SGT with 4F2 cell size shows uniform cell characteristics with a low resistive bit-line path on 3D IC. Parasitic bit-line capacitance of the structure can also be much lower compared to conventional 2D memory cell array or SGT cell array on bulk substrate, which is especially good for memory feature size at or below 10 nm cell node. A combination of 3D memory cell and 3D IC seems to be the ideal memory architecture for the low cost-per- bit of high density memories.