Title :
The TM3270 media-processor data cache
Author :
Van De Waerdt, Jan-Willem ; Vassiliadis, Stamatis ; van Itegem, Jean-Paul ; van Antwerpen, Hans
Author_Institution :
Philips Semicond., San Jose, CA, USA
Abstract :
This paper describes the (micro-) architecture of the TM3270 data cache. We present the cache parameters, such as cache size, associativity, line size and cache policies. We describe the data cache pipeline partitioning and the cache memory structure organization. We introduce "collapsed" and "two-slot" load operations. Furthermore, we introduce a combined software/hardware based technique for prefetching of data into the cache. We use an MPEG2 encoder application for a quantative evaluation of architectural aspects such as data prefetching and show that MPEG2 encoding at 352*288 resolution (CIF) at 25 frames per second can be performed in 33.3 MHz.
Keywords :
cache storage; digital signal processing chips; logic partitioning; pipeline processing; video coding; 33.3 MHz; MPEG2 encoder; TM3270 media processor; cache architecture; cache associativity; cache memory structure organization; cache pipeline partitioning; cache policy; cache size; data cache; data prefetching; Application software; Cache memory; Codecs; Computer architecture; Energy consumption; Hardware; Pipelines; Prefetching; System-on-a-chip; VLIW;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN :
0-7695-2451-6
DOI :
10.1109/ICCD.2005.107
