A BGA package design of a read-out ASIC for GEM imaging detector

The ASIC involved in this paper is a read-out FET array for GEM imaging detector. In the ASIC, 4 (rows) × 8 (columns) units are implemented in an area of 2.5 mm × 2.5 mm. The ASIC is designed with a minimum readout cycle of 100 ns. As a read-out array for imaging detector, the package should be assembled in array form too, thus limits the package size. This paper would introduce the package design for this read-out ASIC, in which the substrate design is mainly focused on. The design limited in specific demands obeys the JEDEC design guide for fine-pitch BGA. The substrate is a 4-layer BT board, with two signal layers and two planes. For the package, designed ball size is 0.3mm. And the package height without attached solder balls is 1.06 +/-0.04 mm. After the process of substrate design and manufacture, die attach, wire bonding, molding, dicing and manual ball attachment, the package has been realized. The practical test for the package has been partially finished. Also the SI simulation is given out to compare with the results practical test brings out. With the results of SI simulation and practical test, the electrical performance of the designed package was evaluated.