Title :
Hybrid CMOS - Memristor based configurable logic block design
Author :
Mane, Pravin S. ; Paul, Namita ; Behera, Nikhilesh ; Sampath, Madankumar ; Ramesha, C.K.
Author_Institution :
Dept. of Electr. & Electron./Instrum., BITS - Pilani, Pilani, India
Abstract :
With increasing demand for greater storage capacity and lower power consumption in memory devices, memristors have emerged as a cutting-edge alternative to transistor based circuitry. After performing a study of the various models for memristor behavior, the TEAM model was used in this paper because of its flexibility to design a hybrid CMOS-memristor based memory crossbar array. The design is substantiated with appropriate simulation results using Cadence. In addition, a lookup table carrying out the function of 1-bit full adder is implemented as an application of memristor based memory. The paper also presents the design of a configurable logic block (CLB), which can be used to fabricate a hybrid CMOS - Memristor FPGA architecture. Based on the memory design, the study evaluates the various advantages of a memristive device over the traditional CMOS approach and shows that the hybrid memory architecture is more efficient.
Keywords :
CMOS memory circuits; adders; field programmable gate arrays; logic design; memristors; table lookup; CLB; Cadence; TEAM model; configurable logic block design; full adder; hybrid CMOS-memristor FPGA architecture; lookup table; memory crossbar array; memory device; memristor behavior; storage capacity; storage capacity 1 bit; CMOS integrated circuits; Equations; Instruments; Mathematical model; Memristors; Semiconductor device modeling; Transistors; Configurable Logic Block(CLB); Field Programmable Gated Array(FPGA); Lookup table(LUT); TEAM model; crossbar array; memristance; memristor; non-volatile memory;
Conference_Titel :
Electronics and Communication Systems (ICECS), 2014 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-2321-2
DOI :
10.1109/ECS.2014.6892532