Simulation of pointer activity in synchronous digital hierarchy networks

Pointer activity in synchronous transport module 1 (STM1) networks is presented based on simulated models of various STM1 network payload configurations. A statistical clock model is used to simulate the effects of clocking instabilities. The clock model used is based upon a root-mean-square (RMS) time interval error (RMSTIE) metric and conforms to the RMSTIE mask as defined by CCITT and other standards committees. Traditional pointer activity studies have been done on a behavioral basis, minimizing byte by byte calculations to reduce simulation time and resolution of results. Additionally, previous studies have examined the effects of constant clock frequency offsets on pointer activity. This study approaches the problem by using byte by byte calculations coupled with a statistical clock model and constant frequency offsets to determine pointer generation and interactions at a level of detail not presented previously. The results of this study are the expected nature of pointer activity in synchronous digital hierarchy (SDH) networks for clock instabilities within the CCITT clock stability specification