A feasibility study of subthreshold SRAM across technology generations

In this paper, we have explored the feasibility of designing an SRAM array in the subthreshold domain of device operation. We have performed a nominal corner analysis of power and stability and a statistical analysis of the different failure probabilities of the subthreshold SRAM. Our analysis shows that subthreshold SRAM gives significant reduction (∼100×) of operating and standby power at iso-performance (∼100MHz) compared to the superthreshold counterpart. However, with increasing intra-die variation owing to technology scaling, the failure probability of subthreshold SRAM increases thereby masking the power benefits.