Layout-aware RF circuit synthesis driven by worst case parasitic corners

We propose a methodology for sizing radio-frequency circuits. Techniques for including layout information during circuit sizing have been presented. The aim of the proposed technique is to obtain parasitic closure at the post-layout validation stage. A two-step approach is adopted for achieving this goal. In the first step, the interconnect parasitic bounds are estimated. In the second step, the parasitic bounds are used to identify the worst case parasitics and the circuit is resized in presence of these parasitics. The proposed approach unlike existing layout-inclusive approaches achieves parasitic closure while not restricting the flexibility and quality of the physical layout. This methodology was applied on RF circuits like low noise amplifiers and the results demonstrate that our technique helps in obtaining robust parasitic aware design solutions.