Title :
Towards finding path delay fault tests with high test efficiency using ZBDDs
Author :
Michael, Maria K. ; Christou, Kyriakos ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Cyprus Univ., Nicosia, Cyprus
Abstract :
A function representing path delay faults (PDFs) together with their nonrobust test cubes is presented. The function is manipulated effectively using zero suppressed binary decision diagrams (ZBDDs) and irredundant sum of products (ISOPs) in ZBDD-based representation, and is derived using a polynomial number, to the circuit size, of standard ZBDD operations. This new data structure can be used effectively during the ATPG process to derive high quality test sets. Experimental results demonstrate that the proposed structure can be implemented efficiently.
Keywords :
automatic test pattern generation; binary decision diagrams; fault simulation; logic testing; ATPG process; data structure; irredundant sum of products; path delay fault tests; polynomial number; zero suppressed binary decision diagrams; Boolean functions; Circuit faults; Circuit testing; Data mining; Data structures; Delay; Encoding; Polynomials; Test pattern generators; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN :
0-7695-2451-6
DOI :
10.1109/ICCD.2005.109
