A Framework for Reliability Assessment in Multilevel Phase-Change Memory

Multilevel-cell (MLC) storage is the preferred way for achieving increased capacity and thus lower cost-per-bit in memory technologies. In phase-change memory (PCM), MLC storage is hampered by noise and resistance drift. In this paper the issue of reliability in MLC PCM devices is addressed at the array level. The purpose of this study is to identify the dominant reliability issues in PCM arrays and to provide a practical methodology to assess the reliability and predict the retention of multilevel states. Experimental data are used to derive and fit simple empirical models which can be used to assess the device reliability over the course of time.