Toward a mixed-signal reconfigurable ASIC for real-time activity recognition

In recent years, there have been increasing interests in context aware sensing based upon ultra-low power wearable sensors. These applications require efficient processing-on-node capabilities to minimise the overall power consumption and wireless transmission bandwidths. In this paper, a novel reconfigurable mixed-signal ASIC designed for real-time activity recognition has been proposed. The system architecture integrates all signal conditioning and data processing circuits onto a single silicon substrate with configurable analogue computing and artificial neuron network-inspired classification blocks. The ASIC is designed using conventional EDA tools and has been fabricated using AMS 0.35mum CMOS technology with a final chip size of 23.8 mm². An on-chip inferencing engine derived from off-chip training data has been developed. Both design considerations and implementation details of the ASIC are discussed. Preliminary simulation results indicate the desired performance of the ASIC for real-time activity classification.