A Ratio-Less 10-Transistor Cell and Static Column Retention Loop Structure for Fully Digital SRAM Design

In this paper, a new memory cell along with a new peripheral circuit for SRAM in ultra fine advanced process technologies is presented. A unique feature of the proposed circuit technique is its circuit design concept to achieve the fully digital ratio-less operation. This enables memory cell design that is free from consideration of the Static Noise Margin (SNM). Furthermore, it enables SRAM function without the restriction of transistor parameter (W/L) settings in circuit design and the dependency on local process variation. To achieve these unique features, we propose (1) a ratio-less memory cell in which the flip/flop loop can be broken in write operation and a push-pull tri-state buffer for secure read operation and (2) the configuration of a static Column Retention Loop (CRL) to prevent loss of memory cell data in the write half-select state. Combining these two key circuit techniques, a new SRAM circuit that is free from design restriction of SNM was developed. A 0.18-μm 1024-bit MOSAIC SRAM TEG consisting of memory cells having all combinations of gate sizes of 10 transistors differing by two orders of magnitude was developed and tested to verify the proposed circuits.