A dual-Vt layout approach for statistical leakage variability minimization in nanometer CMOS

Process parameter variations cause large changes in the delay and the leakage power consumption of scaled nanometer CMOS circuits. In this paper, the problem of leakage power variation minimization in the presence of spatially correlated across-die process variations is addressed. It is shown that with minimal impact on delay, the placement of low-Vt gates in a layout can be performed in such a way to maximize the yield for a specified leakage power upper bound. For the obtained placement of low Vt gates, the layout can then be optimized for other important criteria such as wire length. Simulation of across-die variations for ISCAS benchmarks is performed and guidelines for distributing the low-Vt gates across the die are developed.