• DocumentCode
    2283238
  • Title

    A Scalable, Non-blocking Approach to Transactional Memory

  • Author

    Chafi, Hassan ; Casper, Jared ; Carlstrom, Brian D. ; McDonald, Austen ; Minh, Chi Cao ; Baek, Woongki ; Kozyrakis, Christos ; Olukotun, Kunle

  • Author_Institution
    Comput. Syst. Lab., Stanford Univ., CA
  • fYear
    2007
  • fDate
    10-14 Feb. 2007
  • Firstpage
    97
  • Lastpage
    108
  • Abstract
    Transactional memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, priority inversion, convoying). For TM to be adopted in the long term, not only does it need to deliver on these promises, but it needs to scale to a high number of processors. To date, proposals for scalable TM have relegated livelock issues to user-level contention managers. This paper presents the first scalable TM implementation for directory-based distributed shared memory systems that is livelock free without the need for user-level intervention. The design is a scalable implementation of optimistic concurrency control that supports parallel commits with a two-phase commit protocol, uses write-back caches, and filters coherence messages. The scalable design is based on transactional coherence and consistency (TCC), which supports continuous transactions and fault isolation. A performance evaluation of the design using both scientific and enterprise benchmarks demonstrates that the directory-based TCC design scales efficiently for NUMA systems up to 64 processors
  • Keywords
    cache storage; concurrency control; distributed shared memory systems; parallel programming; performance evaluation; NUMA system; coherence message filtering; directory-based TCC design; directory-based distributed shared memory systems; fault isolation; livelock free; optimistic concurrency control; parallel programming; performance evaluation; transactional coherence and consistency; transactional memory; two-phase commit protocol; write-back caches; Coherence; Concurrency control; Content management; Filters; Large-scale systems; Parallel programming; Programming profession; Proposals; Protocols; System recovery;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture, 2007. HPCA 2007. IEEE 13th International Symposium on
  • Conference_Location
    Scottsdale, AZ
  • Print_ISBN
    1-4244-0805-9
  • Electronic_ISBN
    1-4244-0805-9
  • Type

    conf

  • DOI
    10.1109/HPCA.2007.346189
  • Filename
    4147652