2D process and device simulation of lateral and vertical Si/SiGe high-speed devices

Several adaptations to the properties of SiGe alloys, Si/SiGe heterojunctions and the implementation of all key processes and whole fabrication sequences to a 2D process simulator yield the estimation of the performance potential of novel high-speed device concepts by 2D physically based device simulation. For lateral L/sub G/=0.15 /spl mu/m SiGe MODFETs high drain currents around 450 mA/mm and transconductances up to 290 mS/mm have been calculated. Improved RF cut-off frequencies of f/sub max/=120 GHz and f/sub t/=55 GHz have been estimated for a given device structure in good agreement with experimental reference data. Reduced gate leakage currents and channel lengths below 100 nm are expected by the integration of vertical MOSFET devices. The incorporation of SiGe layers and hetero barriers minimizes the DIBL effect and thus reduces short-channel effects and off-state currents in vertical SiGe Hetero-MOSFETs.